Santa Clara, Calif. — As chip designers, Kaushik Sheth and Egino Sarto struggled to fit silicon into cost-effective packages. Now they're trying to convince other chip designers to adopt a ...

TEMPE, AZ--(Marketwire - Oct 22, 2012) - EPEPS -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced enhancements to its Allegro ® 16.6 ...

Smaller is better when it comes to sterile device package design. The EtO package design is generally either a Tyvek lidded thermoform tray, a Tyvek-poly film pouch, or, for moisture- and ...

Members can download this article in PDF format. Today, advances in semiconductors and ICs are producing ever smaller and denser circuits. With that comes the challenge of efficiently packaging and ...

Santa Cruz, Calif. — For most IC designers, package design must seem like a black art. It's a mysterious process far removed from chip design–until a problem develops and I/Os or bump patterns on the ...

Originally, I started to write this entry about a Sustainable Brand Identity. But as I put pen to paper and fingers to keyboard, I realized that my opening paragraph deserved a bit more attention.